1. Field of the Invention
The invention relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit of a pipeline analog to digital converter and related method.
2. Description of the Prior Art
A pipeline analog to digital converter (pipeline ADC) implemented by the technique of complementary metal oxide semiconductor (CMOS) is able to achieve a sampling rate of 100 M-samples/sec with low power consumption. In general, an analog to digital converter (ADC) utilizes switched capacitors for sampling and holding a signal, which means the pipeline ADC has to switch the capacitor rapidly in order to achieve the high sampling rate. In other words, the pipeline ADC is able to operate at a high sampling rate if the switched capacitor circuit of the pipeline ADC operates quickly.
In general, a switched capacitor circuit couples an input voltage to a capacitor periodically, and the capacitor, which is connected to an input terminal of an amplifier or other circuit, stores the electric charge corresponding to the input voltage periodically, then passes the input voltage to the next stage of the circuit. Please refer to FIG. 1, which is a schematic diagram of a prior art pipeline ADC 10. The pipeline ADC 10 includes a sample-and-hold amplifier (SHA) 12, a plurality of pipeline stages 14, 15, 16, 17, and a logic correction circuit 13. The pipeline ADC 10 converts an analog input signal VIN to a digital output signal DOUT. The resolution of an analog to digital converter is defined by the number of bits of the digital output signal, which is referred to as N. As shown in FIG. 1 the pipeline ADC 10, which has four pipeline stages, is a four-bit analog to digital converter. The SHA 12 is the first stage of the pipeline ADC 10, and is used for sampling the analog input signal VIN and holding the sample voltage VSH as an input signal for the second stage of the pipeline ADC 10. The stage number of pipeline stage 14 following the SHA 12 is N−2, based on the definition of N above, of pipeline ADC 10. In the embodiment of FIG. 1, each pipeline stage outputs a 2-bit signal to the logic correction circuit 13. The bits D11 and D12, D21 and D22, D31 and D32, and D41 and D42 are output signals of the first pipeline stage 14, the second pipeline stage 15, the third pipeline stage 16, and the fourth pipeline stage 17 respectively.
Using the first pipeline stage 14 of the pipeline ADC 10 as an example, please refer to FIG. 2, which is a schematic diagram of the first pipeline stage 14 in FIG. 1. The first pipeline stage 14 includes a residue amplifier 26, a 1.5-bit analog to digital converter (ADC) 22, and a 1.5-bit DAC 24, wherein the 1.5-bit DAC 24 and the residue amplifier 26 combine to form a multiplying DAC (MDAC) 20. The ADC 22 converts the received analog voltage VSH to two bits D11 and D12, and passes the two bits D11, D12 to the 1.5-bit DAC 24 and the logic correction circuit 13 in FIG. 1. Next, the 1.5-bit DAC 24 converts the two bits D11, D12 to an analog signal VDAC1 and passes the analog signal VDAC1 to the signal amplifier 26. Finally, the signal amplifier 26 computes a residue signal Vres1 according to the difference of the output signal VSH of the last stage and the analog signal VDAC1 received from the 1.5-bit DAC 24, and passes the residue signal Vres1 as the input signal of next stage. The other pipeline stages in FIG. 1 have the same function and structure as the first pipeline stage 14 detailed in FIG. 2.
Please refer to FIG. 3, which is a schematic diagram of the MDAC 20 in FIG. 2. As shown in FIG. 3, the input signals VIN+ and VIN− are the differential signals of signal VSH in FIG. 1, signal VDAC1+ and VDAC1− are the differential signals of output signal VDAC1 of the 1.5-bit DAC 24, and signals Vres1+ and Vres1− are both the differential signals of the output signal Vres1 of MDAC 20 and the output signals of the first pipeline stage 14 in FIG. 2. The MDAC 20 is a differential switched capacitor voltage doubler implemented by using a differential operational amplifier. The switches S1, . . . ,S4,S5, . . . ,S8 and S9, S10 are implemented by using transmission gate controlled by clock signals CLK21, CLK22, and CLK12 respectively. The other pipeline stages in FIG. 1 each have a corresponding MDAC with the same function and electrical structure.
Please refer to FIG. 4, which is a schematic diagram of the clock signal for the MDAC of FIG. 3. The clock signals CLK12, CLK21, CLK22 are generated by a clock generator (not shown), wherein the clock signal CLK21 is the inverse of the clock signal CLK22 with a little phase shift, and the clock signal CLK12 is an early-falling form of the clock signal CLK21. When the clock signal CLK21 is pulled up, the input signal VIN− is sampled through the capacitor CS, and during this period the operational amplifier is inactive. When the clock signal CLK22 is pulled up, the reference signal VDAC+ is coupled to the capacitors CS, and Ct, wherein the electrical charge of capacitor CS is equal to the difference of the input signal VIN and the reference signalVDAC1. Then the electrical charge is passed to the operational amplifier and a related output signal Vres1 is generated accordingly. In the worst case, the voltage range of the input signal VIN will be too large, as a result of the swing of the voltage of the input signal VIN, when the procedure of sampling and holding occurs. This phenomenon may cause an overshooting of the output signal Vres1 of the operational amplifier and may reduce the performance of pipeline ADC 10.
In summary, a switched capacitor is usually used to implement the operation of sampling and holding in an ADC, such as the pipeline ADC 10, which includes a SHA 12, a plurality of pipeline stages 14,15,16,17, and a logic correction circuit 13. However, a large overshooting of the output signal can occur when the pipeline ADC samples and holds, if the input signals of each pipeline stage are swinging. Therefore, it is necessary to extend the operation time for switching capacitors, but this also necessarily reduces the efficiency of the pipeline ADC. This problem is the bottleneck to improving the efficiency of the typical pipeline ADC.